1. Field of the Invention
The invention in general relates to the fabrication of integrated circuits, and more particularly to structures and methods for improving the polishing steps in the fabrication of integrated circuits.
2. Statement of the Problem
As is well-known, integrated circuits are generally mass produced by fabricating hundreds of identical circuit patterns on a single semiconducting wafer which is subsequently sawed into hundreds of identical dies or chips. While sometimes referred to as "semiconductor devices", integrated circuits are in fact fabricated from various materials which are either electrically conductive, electrically non-conductive, or electrically semiconductive. Silicon, the most commonly used semiconductor material, can be used in either the single crystal or polycrystalline form. Both forms of silicon may be made conductive by adding impurities to it, which is commonly referred to as "doping". If the doping is with an element such as boron which has one less valence electron than silicon, electron "holes" become the dominant charge carrier and the doped silicon is referred to as P-type silicon. If the doping is with an element such as phosphorus which has one more valence electron than silicon, additional electrons become the dominant charge carriers and the doped silicon is referred to as N-type silicon. Silicon dioxide is also commonly used in integrated circuits as an insulator or dielectric. Its use is so common that in the art is generally referred to as "oxide" without ambiguity.
As indicated above, the properties of silicon are routinely adjusted in integrated circuit technology by adding dopants. Likewise it is common practice to modify other materials, such as conductors or insulators, by adding other components. Or, one material, such as silicon, may be removed or replaced by another. Processes that commonly are used to modify, remove, or deposit a material are ion implantation, sputtering, etching, chemical vapor deposition (CVD) and variations thereof, such as plasma enhanced chemical vapor deposition (PECVD).
The above-discussed processes are often selectively applied to an integrated circuit through the use of a masking process. In a masking process, a photo mask containing the pattern of the structure to be fabricated is created, the wafer is coated with a light-sensitive material called photoresist or resist, the resist-coated wafer is exposed to ultraviolet light through the mask to soften or harden parts of the resist depending on whether positive or negative resist is used, the softened parts of the resist are removed, the wafer is treated by one of the processes discussed above to modify, remove, or replace the part unprotected by the resist, and then the remaining resist is stripped. This masking process permits specific areas of the integrated circuit to be modified, removed or replaced.
Another process commonly used in fabrication of integrated circuits is chemical mechanical polishing (CMP). This process involves chemically etching of a surface while also mechanically grinding or polishing it. The combined action of surface chemical reaction and mechanical polishing allows for a controlled, layer by layer removal of a desired material from the wafer surface, resulting in a preferential removal of protruding surface topography and a planarized wafer surface. CMP is generally accomplished by polishing the wafer front surface against a polishing pad wetted with a slurry comprised of three ingredients: an acidic or basic solvent; an abrasive; and a suspension fluid. The CMP process is generally used to remove undesirable residues remaining from other processes, particularly when it also desirable to create a smooth, planar surface for a subsequent process. In the past few years, CMP has become one of the most effective techniques for planarizing all or a portion of a semiconductor wafer. However, while a good local planarization can be readily achieved in a CMP process, obtaining a complete planarization with good uniformity on the scale of a wafer, or even a die, is not easy. On the wafer scale, the polishing rate often is not uniform from wafer center to edge due to a difference in relative speed between the polishing platen and the wafer carrier at wafer center and edge. On the die scale, planarization is also not easy due to height differences in the oxide layer between different regions on the die, for example between a memory array and the periphery area in a die. On a smaller scale, planarization is difficult because of differences in the height of the oxide layer between, for example, N-well regions and P-well regions. As another example, the material removal rate will vary from place to place on the wafer, depending on the wafer structure and composition. For example, the polishing rate at a wafer trough often differs from that at the other parts of the wafer due to the different slurry distribution and flow at the different areas. These differences are particularly acute in stacked capacitor DRAMs. This lack of homogeneous planarization can result in some material not being removed to a desired final thickness that was intended, i.e under polishing, in some material being removed that it was not intended to remove, i.e. over polishing, or both. Further, since the subsequent processes assume or even require a planar wafer surface, this lack of planarization can alter the properties and parameters of the device. All of these results contribute to defective devices, loss of device yield, and lack of device reliability. Thus there is a need for apparatus and methods to improve the uniformity of planarization in the CMP process.
Since semiconductor devices are becoming more complex in structure and materials, and since the CMP planarization process is dependent on structure and materials, apparatus and techniques that permit the fabrication engineer to control and design the CMP process would be highly desirable.
Generally, a change in one phase of the integrated fabrication process usually impacts other phases. Since integrated circuit fabrication processes are highly complex and require sophisticated equipment, developments of entirely new processes and materials can be quite costly. Thus new apparatus and methods for control of the CMP process that can be incorporated into current fabrication technology would be highly desirable because expensive modification of equipment and processes can be avoided.
3. Solution to the problem
The present invention solves the above problems by providing an integrated fabrication method in which, prior to the CMP process, a portion of the wafer surface is modified in selected areas so that the polishing rate in these areas is altered. For example, areas that tend to be dished after the conventional CMP process, may be modified in a plasma nitridation process to create a material more resistant to polishing, thereby decreasing the polishing rate, with the net result that after the CMP process the dishing is eliminated. Or an area where there are large height differences in a surface to be planarized, the higher area is modified in an ion implantation process to create a material less resistant to polishing, thereby increasing the polishing rate, with the net result that after the CMP process, the overall surface is flat with the height differences eliminated.